// Assign inputs as it happen in real decoder.
assign inputs[0] = _timer[1];
assign inputs[1] = _timer[0];
assign inputs[2] = ~ instr_reg[5];
assign inputs[3] = instr_reg[5];
assign inputs[4] = ~ instr_reg[6];
assign inputs[5] = instr_reg[6];
assign inputs[6] = ~ instr_reg[2];
assign inputs[7] = instr_reg[2];
assign inputs[8] = ~ instr_reg[3];
assign inputs[9] = instr_reg[3];
assign inputs[10] = ~ instr_reg[4];
assign inputs[11] = instr_reg[4];
assign inputs[12] = ~ instr_reg[7];
assign inputs[13] = instr_reg[7];
assign inputs[14] = ~ instr_reg[0];
assign inputs[15] = instr_reg[0] | instr_reg[1]; // IR01
assign inputs[16] = ~ instr_reg[1];
assign inputs[17] = _timer[2];
assign inputs[18] = _timer[3];
assign inputs[19] = _timer[4];
assign inputs[20] = _timer[5];

always #1 @(*) begin

// By default all decoder outputs are zero.
decoder_out = 0; // CHECK : Is it synthesizable ??? Can we just zero it?

case (inputs)
21'b000101100000100100000: decoder_out[0] <= 1'b1;
21'b000000010110001000100: decoder_out[1] <= 1'b1;
21'b000000011010001001000: decoder_out[2] <= 1'b1;
21'b010100011001100100000: decoder_out[3] <= 1'b1;
21'b010101011010100100000: decoder_out[4] <= 1'b1;
21'b010110000001100100000: decoder_out[5] <= 1'b1;

endcase

// Line 128 (IMPL)
decoder_out[128] <= ~ (instr_reg[0] | instr_reg[2] | ~instr_reg[3]);

// Line 129 (Push/Pull)

end