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Design Rule Checks для проверки netlist

Аннотации для определенных участков:

Разбивка все работы на подпроекты:


Все скриншоты доступны http://degate.org/screenshots/

Вот список всех возможностей программы
Features

Degate can handle images, that are very large up to arbitrary large.
It supports OpenGL, but it should be fast enough, even if you avoid the hassle of getting OpenGL running on your computer.
Degate runs on 32 and 64 bit systems, even with low amount of memory.
Degate matches instances of standard cells by a given template.
Degate matches wires and vias. (Okay, the recognition rate and the false acceptance rate highly depends on the image quality.)
You can manually add and remove objects and connect them electrically.
You can define regular and irregular grids.
Degate offers sub-projects. With these you can store overview images and detailed images within a main project.
You can define colors for standard cell ports globally, e. g. to make sure, that clock ports are yellow everywhere.
Degate stores its data in XML format. So you can use external tools for processing. They are also human readable, so that you can understand them without documentation.
You can "bookmark" regions of interest with a feature called "Annotation".
There is support for Design rule checks. This should help to detect problems in the reverse engineered logic model. For example if there is an isolated via next to a wire, then this might indicate an error.
There is an experimental feature for collaborative tracking of wires and vias.
Degate can handle placed standard cells, that are a up-down or left-right flipped versions of a "master" cell.
Auto-saving and recovery of project data. To be honest, there is a reason for having that.
Autonaming of placed standard cells: You can set a name in degate for any object. In most cases it is useful, if you set a name for placed standard cells, that somehow indicates, where the cell is placed. Therefore the autonaming feature was introduced to automatically assign names in the format x.y, where x indicates the column and y indicates the row of the placement.
You can write your own tools for the matching of wires and vias (e. g. in Matlab) and interface your script with degate.
You can document standard cell's behavior with VHDL, Verilog and even plain text. Degate can also generate VHDL and Verilog implementation stubs.
A circuit's netlist is a description of its structural domain. The netlist is derivable from the logic model. If you have a behavioural description of all gates, it is possible to generate rolled out VHDL or Verilog code. From that you can simulate and resynthesize the circuit. The export of Verilog netlists is already implemented..